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Operating Systems/Input Output.md

@@ -86,3 +86,40 @@ An alternative mode is to have the device controller send the word to DMA contro
 
 ![](Pasted%20image%2020250505195901.png)
 
+
+![](Pasted%20image%2020250505200028.png)
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+
+### Handling interrupts
+- Microprogram or hardware checked to see if there was an interrupt pending.
+- Instruction cycle:
+	- Fethc
+	- Decode
+	- Read operands
+	- Execute
+	- Store 
+	- Check for interrupts
+
+This can be pipelined
+
+### Precise interrupts
+1. PC is saved in a known place
+2. All instructions before the one pointed to by the PC have completed
+3. No instruction beyond the current one has vfinished
+4. Execution state is known
+
+An interrupt that doesn't meet the above requirements is called **imprecise**
+
+![](Pasted%20image%2020250505200548.png)
+
+## Clocks
+![](Pasted%20image%2020250505201102.png)
+
+> [!IMPORTANT]
+> Watchdog timers **ARE clocks**
+
+
+
+## Mass Storage
+Secondary storage for modern computers and shit.
+