Notes/Operating Systems/Input Output.md

type

type
theoretical

I/O devices can be divided into two categories:

• Block devices -> store information in fixed-size blocks, each one with its own address
• Character devices -> deliver or accepts a stream of characters (no regard to any structure)
  • Obviously, it is not addressable

They have components:

• Mechanical -> the thing (sensor blah blah)
• Electronic -> the controller
  • Converts serial bit stream to block of bytes
  • Perform error detection
  • Make available to main memory

Memory-Mapped I/O

Controllers have a few registers that are used for communcation with the CPU. Writing in these registers, the OS can command the device to perform an action. By reading the registers, it can tell its state.

Important

In memory-mapped I/O each control register is assigned a unique memory address to which no memory is assigned. › In most systems, the assigned addresses are at or near the top of the address space.

Advantages

• Special I/O instructions are needed to read and write the control registers
• Simple device driver
• With memory-mapped I/O, no special protection mechanism is needed to keep user processes from performing I/O.
• If each device has its control registers on a different page of the address space, the operating system can give a user control over specific devices but not others by simply including the desired pages in its page table.

Disadvantages

• Caching the page of a device control register would be a problem
  • The DCRs are cached => references would just take value from cache (stale data)
  • Infinite loop is possible, since the software would never know whether the device is ready
• Single bus -> everyone looks at every address
• One address space, then all memory modules and all I/O devices must examine all memory references to see which ones to respond to

DMA

Requesting one byte at a time from an I/O controller wastes the CPU’s time. Instead, DMA (Direct Memory Access) is often used

DMA controllers has access to the system bus independently of the CPU Includes registers that can be written and read by the CPU:

• Memory address register
• Byte count register
• One or more control registers to specify the I/O port to use, direction of transfer, transfer unit, number of bytes in one burst

Accessing BUS

• Word-at-a-time -> request the transfer of one word and gets bus, CPU waits (cycle stealing)
• block mode -> acquire the bus, issue a series of transfers and releast. burst mode.

Accessing memory

We can do main memory -> fly-by mode. An alternative mode is to have the device controller send the word to DMA controller, which the issues a bus request to write the word.

Device Internal Buffer

• Read the data into its internal buffer first
  • Verify the checksum (error checking) before starting a transfer
  • The bits keep arriving at a constant rate, whether the controller is ready for them or not
• DMA transfer to memory is not time critical

[!IMPORTANT] No DMA Not all computers use DMA, CPU is often far faster than the DMA controller and can do the job muuuch faster.

Interrupts

1. I/O device requests a service, it causes an interrupt, asserting a signal on a bus line assigned to it
2. Signal is detected by the interrupt controller chip
3. If no other interrupts are pending, interrupt controller handles interrupt
   • Otherwise, we do priority, with the device sending interrupt signal until its serviced
4. Controller puts a number on the address lines specifying which device wants attention
5. Interrupt causes CPU to stop what it is doing
6. Number on address lines is used as an indexed into a table called the interrupt vector

Handling interrupts

• Microprogram or hardware checked to see if there was an interrupt pending.
• Instruction cycle:
  • Fethc
  • Decode
  • Read operands
  • Execute
  • Store
  • Check for interrupts

This can be pipelined

Precise interrupts

1. PC is saved in a known place
2. All instructions before the one pointed to by the PC have completed
3. No instruction beyond the current one has vfinished
4. Execution state is known

An interrupt that doesn't meet the above requirements is called imprecise

Clocks

Important

Watchdog timers ARE clocks

Mass Storage

Secondary storage for modern computers and shit.